| Verification Methodology Manual |
| version 1.1.1 |
| |
| (C) Copyright 2004-2009 Synopsys, Inc. |
| All Rights Reserved Worldwide |
| |
| |
| The SystemVerilog code in this distribution was developped using |
| VCS2009.06 and no special action need to be taken if you are using |
| the 2009.06 release of VCS. |
| |
| Howeber, it may be a good idea to define the symbol `VCS2009_06 when |
| compiling the SystemVerilog source code to support possible required |
| work-arounds in future release of this distribution. This can be |
| accomplished from the command line using the +define option as shown below: |
| |
| % vcs -sverilog +define+VCS2009_06 +incdir=$VMM_HOME/sv ... |
| |
