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refs/heads/mwk/xilinx-dsp48-sim
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ecp5
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abc9_5g_nowide.lut
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# ECP5-5G LUT library for ABC
# Note that ECP5 architecture assigns difference
# in LUT input delay to interconnect, so this is
# considered too
# Simple LUTs
# area D C B A
1
1
141
2
1
141
275
3
1
141
275
379
4
1
141
275
379
379