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foss-fpga-tools / third_party / yosys / refs/heads/mwk/xilinx-dsp48-sim / . / techlibs / ecp5
tree: 172afdc1542e50182b00b0705d849fccbbf432fe [path history] [tgz]
  1. tests/
  2. .gitignore
  3. abc9_5g.box
  4. abc9_5g.lut
  5. abc9_5g_nowide.lut
  6. abc9_map.v
  7. abc9_model.v
  8. abc9_unmap.v
  9. arith_map.v
  10. bram.txt
  11. brams_connect.py
  12. brams_init.py
  13. brams_map.v
  14. cells_bb.v
  15. cells_ff.vh
  16. cells_io.vh
  17. cells_map.v
  18. cells_sim.v
  19. dsp_map.v
  20. ecp5_ffinit.cc
  21. ecp5_gsr.cc
  22. latches_map.v
  23. lutram.txt
  24. lutrams_map.v
  25. Makefile.inc
  26. synth_ecp5.cc