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foss-fpga-tools
/
third_party
/
yosys
/
refs/heads/mwk/xilinx-dsp48-sim
/
.
/
techlibs
/
ecp5
/
abc9_model.v
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// ---------------------------------------
(*
abc9_box_id
=
2
*)
module
\$__ABC9_DPR16X4_COMB
(
input
[
3
:
0
]
A
,
S
,
output
[
3
:
0
]
Y
);
endmodule
