Sign in
foss-fpga-tools
/
third_party
/
yosys
/
refs/heads/mwk/xilinx-dsp48-sim
/
.
/
techlibs
/
ecp5
/
abc9_unmap.v
blob: 9ae143c467b192fb716b035b1cf8ffff66dce336 [
file
] [
log
] [
blame
] [
edit
]
// ---------------------------------------
module
\$__ABC9_DPR16X4_COMB
(
input
[
3
:
0
]
A
,
S
,
output
[
3
:
0
]
Y
);
assign Y
=
A
;
endmodule