| commit | 0fb95e54c6ac2270bff620285c73a6f9e95a61e3 | [log] [tgz] |
|---|---|---|
| author | Alessandro Comodi <44773360+acomodi@users.noreply.github.com> | Mon Nov 30 12:17:57 2020 +0100 |
| committer | GitHub <noreply@github.com> | Mon Nov 30 12:17:57 2020 +0100 |
| tree | 70111718d73851950fe0bcf05c0f27d7c1e77030 | |
| parent | f05a56d2cec2ac9304aaeb613b0d44d3d0187c32 [diff] | |
| parent | 3aa88ede1cab4d4dfde79bd0f285a043d1249bf5 [diff] |
Merge pull request #57 from antmicro/sdc_skip_clocks_on_dangling_wires SDC: Skip adding clocks on dangling wires
This repository contains plugins for Yosys developed as part of the SymbiFlow project.