Merge pull request #519 from antmicro/kr/fix_unsized

systemverilog-plugin: fix parsing unsized unbased consts

systemverilog-plugin/tests/break_continue/break_continue.tcl

diff --git a/systemverilog-plugin/tests/break_continue/break_continue.tcl b/systemverilog-plugin/tests/break_continue/break_continue.tcl
index ce1b4cf..d496367 100644
--- a/systemverilog-plugin/tests/break_continue/break_continue.tcl
+++ b/systemverilog-plugin/tests/break_continue/break_continue.tcl
@@ -2,7 +2,7 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 # Testing simple round-trip

systemverilog-plugin/tests/counter/counter.tcl

diff --git a/systemverilog-plugin/tests/counter/counter.tcl b/systemverilog-plugin/tests/counter/counter.tcl
index 1904a4b..28a4447 100644
--- a/systemverilog-plugin/tests/counter/counter.tcl
+++ b/systemverilog-plugin/tests/counter/counter.tcl
@@ -2,7 +2,7 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 # Testing simple round-trip

systemverilog-plugin/tests/debug-flag/debug-flag.tcl

diff --git a/systemverilog-plugin/tests/debug-flag/debug-flag.tcl b/systemverilog-plugin/tests/debug-flag/debug-flag.tcl
index 17b84db..3b3a568 100644
--- a/systemverilog-plugin/tests/debug-flag/debug-flag.tcl
+++ b/systemverilog-plugin/tests/debug-flag/debug-flag.tcl
@@ -2,7 +2,7 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 # Testing simple round-trip

systemverilog-plugin/tests/defaults/defaults.tcl

diff --git a/systemverilog-plugin/tests/defaults/defaults.tcl b/systemverilog-plugin/tests/defaults/defaults.tcl
index 14750d7..804d2e5 100644
--- a/systemverilog-plugin/tests/defaults/defaults.tcl
+++ b/systemverilog-plugin/tests/defaults/defaults.tcl
@@ -2,7 +2,7 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 # Define forbidden value

systemverilog-plugin/tests/defines/defines.tcl

diff --git a/systemverilog-plugin/tests/defines/defines.tcl b/systemverilog-plugin/tests/defines/defines.tcl
index f1ccc67..14b37ad 100644
--- a/systemverilog-plugin/tests/defines/defines.tcl
+++ b/systemverilog-plugin/tests/defines/defines.tcl
@@ -2,7 +2,7 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 systemverilog_defines -DPONA

systemverilog-plugin/tests/formal/formal.tcl

diff --git a/systemverilog-plugin/tests/formal/formal.tcl b/systemverilog-plugin/tests/formal/formal.tcl
index 2eba6ac..b2590d3 100644
--- a/systemverilog-plugin/tests/formal/formal.tcl
+++ b/systemverilog-plugin/tests/formal/formal.tcl
@@ -2,7 +2,7 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 read_systemverilog -o $TMP_DIR -formal $::env(DESIGN_TOP).v

systemverilog-plugin/tests/report-flag/report-flag.tcl

diff --git a/systemverilog-plugin/tests/report-flag/report-flag.tcl b/systemverilog-plugin/tests/report-flag/report-flag.tcl
index df1b087..d49a46b 100644
--- a/systemverilog-plugin/tests/report-flag/report-flag.tcl
+++ b/systemverilog-plugin/tests/report-flag/report-flag.tcl
@@ -2,7 +2,7 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 # Testing simple round-trip

systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl

diff --git a/systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl b/systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl
index 82cbfc9..46b029a 100644
--- a/systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl
+++ b/systemverilog-plugin/tests/separate-compilation/separate-compilation.tcl
@@ -2,7 +2,7 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 # Testing simple round-trip

systemverilog-plugin/tests/translate_off/translate_off.tcl

diff --git a/systemverilog-plugin/tests/translate_off/translate_off.tcl b/systemverilog-plugin/tests/translate_off/translate_off.tcl
index 15e411b..d836d1e 100644
--- a/systemverilog-plugin/tests/translate_off/translate_off.tcl
+++ b/systemverilog-plugin/tests/translate_off/translate_off.tcl
@@ -2,7 +2,7 @@
 if { [info procs read_uhdm] == {} } { plugin -i systemverilog }
 yosys -import  ;# ingest plugin commands
 
-set TMP_DIR ::env(TEST_OUTPUT_PREFIX)/tmp
+set TMP_DIR $::env(TEST_OUTPUT_PREFIX)/tmp
 file mkdir $TMP_DIR
 
 read_systemverilog -o $TMP_DIR $::env(DESIGN_TOP).v