docs: Improving the examples from VtR documentation. * Renamed the files. * Adding diagrams / images. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
diff --git a/docs/tests/vtr-examples.rst b/docs/tests/vtr-examples.rst index ebec334..33e94d9 100644 --- a/docs/tests/vtr-examples.rst +++ b/docs/tests/vtr-examples.rst
@@ -8,6 +8,6 @@ .. toctree:: - vtr/fig28-lutff-pair.md - vtr/fig41-full-adder.md - vtr/fig42-dff.md + vtr/lutff-pair.md + vtr/full-adder.md + vtr/dff.md
diff --git a/tests/vtr/dff/README.md b/tests/vtr/dff/README.md new file mode 100644 index 0000000..c4c2fe3 --- /dev/null +++ b/tests/vtr/dff/README.md
@@ -0,0 +1,28 @@ +# Classical D-Flip-Flop test + +An example of the classical D-Flip-Flop. + +This is shown in `Figure 43 - DFF` of the +["Sequential block (no internal paths)"](https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#sequential-block-no-internal-paths) +section in the +[Primitive Block Timing Modeling Tutorial](https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#) +of the +[Verilog to Routing documentation](https://docs.verilogtorouting.org) +and reproduced below; + +>  +> *Fig. 43 DFF* + +## Clock associations inference + + - [ ] automatic inference is signal is associated with any clock and include the info in the model + - [ ] automatic clock detection (signals named `clk` are considered as clocks) + +## Blackbox detection + + - [ ] model of the leaf `pb_type` is generated + - [ ] leaf `pb_type` XML is generated + +## Timings + + - [ ] all the timings defined for wires with attributes should be included in `pb_type` XML
diff --git a/tests/vtr/fig42-dff/dff.sim.v b/tests/vtr/dff/dff.sim.v similarity index 100% rename from tests/vtr/fig42-dff/dff.sim.v rename to tests/vtr/dff/dff.sim.v
diff --git a/tests/vtr/dff/dff.svg b/tests/vtr/dff/dff.svg new file mode 100644 index 0000000..f7bea2e --- /dev/null +++ b/tests/vtr/dff/dff.svg
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diff --git a/tests/vtr/fig42-dff/golden.model.xml b/tests/vtr/dff/golden.model.xml similarity index 100% rename from tests/vtr/fig42-dff/golden.model.xml rename to tests/vtr/dff/golden.model.xml
diff --git a/tests/vtr/fig28-lutff-pair/README.md b/tests/vtr/fig28-lutff-pair/README.md deleted file mode 100644 index 49792b3..0000000 --- a/tests/vtr/fig28-lutff-pair/README.md +++ /dev/null
@@ -1,15 +0,0 @@ -# `fig28-lutff-pair` test - -This directory contains test for the `v2x_to_model.py` and `v2x_to_pb_type` tools. -The tests use models defined in ff, lut and omux tests. -Those tests should check the following features: - -## Blackbox detection - - - [ ] model of the leaf pb\_type is generated - - [ ] leaf pb\_type xml is generated - - [ ] all dependency models and pb\_types are included in the output files - -## Carry chain inference - - - [ ] pack\_pattern inference - pack\_patterns defined on wires with `pack` attributes should be propagated to pb\_type xmls
diff --git a/tests/vtr/fig28-lutff-pair/lut/README.md b/tests/vtr/fig28-lutff-pair/lut/README.md deleted file mode 100644 index 0781ed1..0000000 --- a/tests/vtr/fig28-lutff-pair/lut/README.md +++ /dev/null
@@ -1,18 +0,0 @@ -# `fig28-lutff-pair` - `lut` test - -This directory contains test for the `v2x_to_model.py` and `v2x_to_pb_type` tools. -Those tests should check the following features: - -## Blackbox detection - - - [ ] model of the leaf pb\_type is generated - - [ ] leaf pb\_type xml is generated - - [ ] all dependency models and pb\_types are included in the output files - -## Carry chain inference - - - [ ] pack\_pattern inference - pack\_patterns defined on wires with `pack` attributes should be propagated to pb\_type xmls - -## Timings - - - [ ] timings defined for wires with `DELAY_MATRIX` attribute should be propagated to pb\_type xml
diff --git a/tests/vtr/fig41-full-adder/README.md b/tests/vtr/fig41-full-adder/README.md deleted file mode 100644 index e08513f..0000000 --- a/tests/vtr/fig41-full-adder/README.md +++ /dev/null
@@ -1,17 +0,0 @@ -# `fig41-full-adder` test - -This directory contains test for the blackbox detection for the -`v2x_to_model.py` and `v2x_to_pb_type` tools. - -## Detection of combinational connections - - - [ ] output has combinational connection with input - -## Blackbox detection - - - [ ] model of the leaf pb\_type is generated - - [ ] leaf pb\_type xml is generated - -## Timings - - - [ ] all the timings defined for wires with attributes should be included in pb\_type xml
diff --git a/tests/vtr/fig42-dff/README.md b/tests/vtr/fig42-dff/README.md deleted file mode 100644 index 0cbaf6f..0000000 --- a/tests/vtr/fig42-dff/README.md +++ /dev/null
@@ -1,17 +0,0 @@ -# `fig42-dff` test - -This directory contains tests for the `v2x_to_model.py` and `v2x_to_pb_type` tools. - -## Clock associations inference - - - [ ] automatic inference is signal is associated with any clock and include the info in the model - - [ ] automatic clock detection (signals named `clk` are considered as clocks) - -## Blackbox detection - - - [ ] model of the leaf pb\_type is generated - - [ ] leaf pb\_type xml is generated - -## Timings - - - [ ] all the timings defined for wires with attributes should be included in pb\_type xml
diff --git a/tests/vtr/full-adder/README.md b/tests/vtr/full-adder/README.md new file mode 100644 index 0000000..08f302d --- /dev/null +++ b/tests/vtr/full-adder/README.md
@@ -0,0 +1,27 @@ +# Full Adder Example + +An example of the classical combinational ["full adder"](https://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder) circuit. + +This is shown in `Figure 41 - Full Adder` of the +["Combinational block"](https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#combinational-block) +section in the +[Primitive Block Timing Modeling Tutorial](https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#) +of the +[Verilog to Routing documentation](https://docs.verilogtorouting.org) +and reproduced below; + +>  +> *Fig. 41 Full Adder* + +## Detection of combinational connections + + - [ ] output has combinational connection with input + +## Blackbox detection + + - [ ] model of the leaf `pb_type` is generated + - [ ] leaf `pb_type` XML is generated + +## Timings + + - [ ] all the timings defined for wires with attributes should be included in `pb_type` XML
diff --git a/tests/vtr/fig41-full-adder/adder.sdf b/tests/vtr/full-adder/adder.sdf similarity index 100% rename from tests/vtr/fig41-full-adder/adder.sdf rename to tests/vtr/full-adder/adder.sdf
diff --git a/tests/vtr/fig41-full-adder/adder.sim.v b/tests/vtr/full-adder/adder.sim.v similarity index 100% rename from tests/vtr/fig41-full-adder/adder.sim.v rename to tests/vtr/full-adder/adder.sim.v
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diff --git a/tests/vtr/fig41-full-adder/golden.model.xml b/tests/vtr/full-adder/golden.model.xml similarity index 100% rename from tests/vtr/fig41-full-adder/golden.model.xml rename to tests/vtr/full-adder/golden.model.xml
diff --git a/tests/vtr/fig41-full-adder/golden.pb_type.xml b/tests/vtr/full-adder/golden.pb_type.xml similarity index 100% rename from tests/vtr/fig41-full-adder/golden.pb_type.xml rename to tests/vtr/full-adder/golden.pb_type.xml
diff --git a/tests/vtr/lutff-pair/README.md b/tests/vtr/lutff-pair/README.md new file mode 100644 index 0000000..dbd5796 --- /dev/null +++ b/tests/vtr/lutff-pair/README.md
@@ -0,0 +1,20 @@ +# LUT with FlipFlop Example + +An example of the classical LUT with FlipFlop pair. + +This is shown in `Figure 28` of the +[Architecture Reference section of the Verilog to Routing Documentation](https://docs.verilogtorouting.org/en/latest/arch/reference) +and reproduced below; + +>  +> *Fig. 28 Pack Pattern Example.* + +## Blackbox detection + + - [ ] model of the leaf `pb_type` is generated + - [ ] leaf `pb_type` XML is generated + - [ ] all dependency models and `pb_type`s are included in the output files + +## Carry chain inference + + - [ ] `pack_pattern` inference - `pack_pattern`s defined on wires with `pack` attributes should be propagated to `pb_type` XMLs
diff --git a/tests/vtr/fig28-lutff-pair/ff/ff.sim.v b/tests/vtr/lutff-pair/ff/ff.sim.v similarity index 100% rename from tests/vtr/fig28-lutff-pair/ff/ff.sim.v rename to tests/vtr/lutff-pair/ff/ff.sim.v
diff --git a/tests/vtr/fig28-lutff-pair/ff/golden.model.xml b/tests/vtr/lutff-pair/ff/golden.model.xml similarity index 100% rename from tests/vtr/fig28-lutff-pair/ff/golden.model.xml rename to tests/vtr/lutff-pair/ff/golden.model.xml
diff --git a/tests/vtr/fig28-lutff-pair/ff/golden.pb_type.xml b/tests/vtr/lutff-pair/ff/golden.pb_type.xml similarity index 100% rename from tests/vtr/fig28-lutff-pair/ff/golden.pb_type.xml rename to tests/vtr/lutff-pair/ff/golden.pb_type.xml
diff --git a/tests/vtr/fig28-lutff-pair/golden.model.xml b/tests/vtr/lutff-pair/golden.model.xml similarity index 100% rename from tests/vtr/fig28-lutff-pair/golden.model.xml rename to tests/vtr/lutff-pair/golden.model.xml
diff --git a/tests/vtr/fig28-lutff-pair/golden.pb_type.xml b/tests/vtr/lutff-pair/golden.pb_type.xml similarity index 100% rename from tests/vtr/fig28-lutff-pair/golden.pb_type.xml rename to tests/vtr/lutff-pair/golden.pb_type.xml
diff --git a/tests/vtr/fig28-lutff-pair/lut/golden.model.xml b/tests/vtr/lutff-pair/lut/golden.model.xml similarity index 100% rename from tests/vtr/fig28-lutff-pair/lut/golden.model.xml rename to tests/vtr/lutff-pair/lut/golden.model.xml
diff --git a/tests/vtr/fig28-lutff-pair/lut/golden.pb_type.xml b/tests/vtr/lutff-pair/lut/golden.pb_type.xml similarity index 100% rename from tests/vtr/fig28-lutff-pair/lut/golden.pb_type.xml rename to tests/vtr/lutff-pair/lut/golden.pb_type.xml
diff --git a/tests/vtr/fig28-lutff-pair/lut/lut4.sim.v b/tests/vtr/lutff-pair/lut/lut4.sim.v similarity index 100% rename from tests/vtr/fig28-lutff-pair/lut/lut4.sim.v rename to tests/vtr/lutff-pair/lut/lut4.sim.v
diff --git a/tests/vtr/lutff-pair/lutff-pair.png b/tests/vtr/lutff-pair/lutff-pair.png new file mode 100644 index 0000000..e0f9c36 --- /dev/null +++ b/tests/vtr/lutff-pair/lutff-pair.png Binary files differ
diff --git a/tests/vtr/fig28-lutff-pair/pair.sim.v b/tests/vtr/lutff-pair/pair.sim.v similarity index 100% rename from tests/vtr/fig28-lutff-pair/pair.sim.v rename to tests/vtr/lutff-pair/pair.sim.v
