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foss-fpga-tools/python-symbiflow-v2x/60850efef7f5ac37adbd0777581329e41cb83181^1..60850efef7f5ac37adbd0777581329e41cb83181/.
commit
60850efef7f5ac37adbd0777581329e41cb83181
[log]
author
Tim Ansell <me@mith.ro>
Tue Apr 14 22:25:42 2020 -0700
committer
GitHub <noreply@github.com>
Tue Apr 14 22:25:42 2020 -0700
tree
a68c26849b9f0832f959c6cb069ac3bdb45d4bbb
parent
037d50d09362cdcec5a109e8509a743f787f0e90 [diff]
parent
80a5eadfb6bb23e30ca407d16514e6afd331332b [diff]
Merge pull request #39 from daniellimws/license-headers

Add license header to top of all code files
diff --git a/tests/carry/carry.sim.v b/tests/carry/carry.sim.v
index 9263abd..e49685d 100644
--- a/tests/carry/carry.sim.v
+++ b/tests/carry/carry.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `default_nettype none
 `include "cblock/cblock.sim.v"
 

diff --git a/tests/carry/cblock/cblock.sim.v b/tests/carry/cblock/cblock.sim.v
index b73ddbb..75f6f36 100644
--- a/tests/carry/cblock/cblock.sim.v
+++ b/tests/carry/cblock/cblock.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `default_nettype none
 
 (* whitebox *)

diff --git a/tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v b/tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
index a1e60c2..6a6a355 100644
--- a/tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v
+++ b/tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v

@@ -1,4 +1,14 @@
 /*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
+/*
  * `input wire a` should be detected as a clock because it drives the flip
  * flop.
  */

diff --git a/tests/clocks/dff_one_clock/dff_one_clock.sim.v b/tests/clocks/dff_one_clock/dff_one_clock.sim.v
index d6e2c39..4549365 100644
--- a/tests/clocks/dff_one_clock/dff_one_clock.sim.v
+++ b/tests/clocks/dff_one_clock/dff_one_clock.sim.v

@@ -1,4 +1,14 @@
 /*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
+/*
  * `input wire a` should be detected as a clock because it drives the flip
  * flop.
  */

diff --git a/tests/clocks/dff_two_clocks/dff_two_clocks.sim.v b/tests/clocks/dff_two_clocks/dff_two_clocks.sim.v
index c9bcb0f..4d27af3 100644
--- a/tests/clocks/dff_two_clocks/dff_two_clocks.sim.v
+++ b/tests/clocks/dff_two_clocks/dff_two_clocks.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 module BLOCK(c1, c2, a, b, c, o1, o2);
 	input wire c1;
 	input wire c2;

diff --git a/tests/clocks/input_attr_clock/input_attr_clock.sim.v b/tests/clocks/input_attr_clock/input_attr_clock.sim.v
index 819cb8f..57b744d 100644
--- a/tests/clocks/input_attr_clock/input_attr_clock.sim.v
+++ b/tests/clocks/input_attr_clock/input_attr_clock.sim.v

@@ -1,4 +1,14 @@
 /*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
+/*
  * `input wire a` should be detected as a clock because of the `(* CLOCK *)`
  * attribute.
  */

diff --git a/tests/clocks/input_attr_not_clock/block.sim.v b/tests/clocks/input_attr_not_clock/block.sim.v
index f87f8b2..856cdd0 100644
--- a/tests/clocks/input_attr_not_clock/block.sim.v
+++ b/tests/clocks/input_attr_not_clock/block.sim.v

@@ -1,4 +1,14 @@
 /*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
+/*
  * `input wire a` should be detected as a clock because it drives the flip
  * flop. However, it has the attribute CLOCK set to 0 which should force it
  * to be a regular input.

diff --git a/tests/clocks/input_named_clk/input_named_clk.sim.v b/tests/clocks/input_named_clk/input_named_clk.sim.v
index 7d5b619..e730c87 100644
--- a/tests/clocks/input_named_clk/input_named_clk.sim.v
+++ b/tests/clocks/input_named_clk/input_named_clk.sim.v

@@ -1,4 +1,14 @@
 /*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
+/*
  * `input wire clk` should be detected as a clock despite this being a black
  * box module.
  */

diff --git a/tests/clocks/input_named_rdclk/input_named_rdclk.sim.v b/tests/clocks/input_named_rdclk/input_named_rdclk.sim.v
index 70d827a..9ebb2cf 100644
--- a/tests/clocks/input_named_rdclk/input_named_rdclk.sim.v
+++ b/tests/clocks/input_named_rdclk/input_named_rdclk.sim.v

@@ -1,4 +1,14 @@
 /*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
+/*
  * `input wire rdclk` should be detected as a clock despite this being a black
  * box module.
  */

diff --git a/tests/clocks/input_named_regex/block.sim.v b/tests/clocks/input_named_regex/block.sim.v
index 3870d30..bbb5838 100644
--- a/tests/clocks/input_named_regex/block.sim.v
+++ b/tests/clocks/input_named_regex/block.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* whitebox *)
 module BLOCK(
     input  wire clk,

diff --git a/tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v b/tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v
index 076d630..e8146e5 100644
--- a/tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v
+++ b/tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v

@@ -1,4 +1,14 @@
 /*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
+/*
  * `input wire rdclk` and `input wire wrclk` should be detected as a clock
  * despite this being a black box module.
  */

diff --git a/tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v b/tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v
index 42899f8..6ce6f50 100644
--- a/tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v
+++ b/tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v

@@ -1,4 +1,14 @@
 /*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
+/*
  * `output wire rdclk` and `output wire wrclk` should be detected as a clock
  * despite this being a black box module.
  */

diff --git a/tests/clocks/output_attr_clock/output_attr_clock.sim.v b/tests/clocks/output_attr_clock/output_attr_clock.sim.v
index bdf4747..fc3b6bc 100644
--- a/tests/clocks/output_attr_clock/output_attr_clock.sim.v
+++ b/tests/clocks/output_attr_clock/output_attr_clock.sim.v

@@ -1,4 +1,14 @@
 /*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
+/*
  * `output wire o` should be detected as a clock because of the `(* CLOCK *)`
  * attribute.
  */

diff --git a/tests/clocks/output_named_clk/output_named_clk.sim.v b/tests/clocks/output_named_clk/output_named_clk.sim.v
index fcf775b..331a5a4 100644
--- a/tests/clocks/output_named_clk/output_named_clk.sim.v
+++ b/tests/clocks/output_named_clk/output_named_clk.sim.v

@@ -1,4 +1,14 @@
 /*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
+/*
  * `output wire clk` should be detected as a clock despite this being a black
  * box module.
  */

diff --git a/tests/clocks/output_named_rdclk/output_named_rdclk.sim.v b/tests/clocks/output_named_rdclk/output_named_rdclk.sim.v
index 4b72b6f..ef20d94 100644
--- a/tests/clocks/output_named_rdclk/output_named_rdclk.sim.v
+++ b/tests/clocks/output_named_rdclk/output_named_rdclk.sim.v

@@ -1,4 +1,14 @@
 /*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
+/*
  * `output wire rdclk` should be detected as a clock despite this being a black
  * box module.
  */

diff --git a/tests/dsp/dsp_combinational/dsp_combinational.sim.v b/tests/dsp/dsp_combinational/dsp_combinational.sim.v
index bbfa953..635eef3 100644
--- a/tests/dsp/dsp_combinational/dsp_combinational.sim.v
+++ b/tests/dsp/dsp_combinational/dsp_combinational.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `ifndef DSP_COMB
 `define DSP_COMB
 (* whitebox *)

diff --git a/tests/dsp/dsp_in_registered/dsp_in_registered.sim.v b/tests/dsp/dsp_in_registered/dsp_in_registered.sim.v
index b940e44..930674d 100644
--- a/tests/dsp/dsp_in_registered/dsp_in_registered.sim.v
+++ b/tests/dsp/dsp_in_registered/dsp_in_registered.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "../../vtr/dff/dff.sim.v"
 `include "../dsp_combinational/dsp_combinational.sim.v"
 

diff --git a/tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v b/tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v
index 2417b82..87b0164 100644
--- a/tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v
+++ b/tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "../../vtr/dff/dff.sim.v"
 `include "../dsp_combinational/dsp_combinational.sim.v"
 

diff --git a/tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v b/tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v
index bb73b32..4a928a9 100644
--- a/tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v
+++ b/tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "../../vtr/dff/dff.sim.v"
 `include "../dsp_combinational/dsp_combinational.sim.v"
 

diff --git a/tests/dsp/dsp_modes/dsp_modes.sim.v b/tests/dsp/dsp_modes/dsp_modes.sim.v
index cd7f69b..f93b858 100644
--- a/tests/dsp/dsp_modes/dsp_modes.sim.v
+++ b/tests/dsp/dsp_modes/dsp_modes.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "../dsp_combinational/dsp_combinational.sim.v"
 `include "../dsp_inout_registered/dsp_inout_registered.sim.v"
 `include "../dsp_in_registered/dsp_in_registered.sim.v"

diff --git a/tests/dsp/dsp_out_registered/dsp_out_registered.sim.v b/tests/dsp/dsp_out_registered/dsp_out_registered.sim.v
index c9f7b74..f6c8cfa 100644
--- a/tests/dsp/dsp_out_registered/dsp_out_registered.sim.v
+++ b/tests/dsp/dsp_out_registered/dsp_out_registered.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "../../vtr/dff/dff.sim.v"
 `include "../dsp_combinational/dsp_combinational.sim.v"
 

diff --git a/tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v b/tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v
index 3ffc3b7..3ee235e 100644
--- a/tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v
+++ b/tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "../../vtr/dff/dff.sim.v"
 `include "../dsp_combinational/dsp_combinational.sim.v"
 

diff --git a/tests/internal_conn/child/child.sim.v b/tests/internal_conn/child/child.sim.v
index e6aee44..9867f80 100644
--- a/tests/internal_conn/child/child.sim.v
+++ b/tests/internal_conn/child/child.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* blackbox *)
 module CHILD(
   input  wire I,

diff --git a/tests/internal_conn/parent.sim.v b/tests/internal_conn/parent.sim.v
index f837c7b..6d10ee1 100644
--- a/tests/internal_conn/parent.sim.v
+++ b/tests/internal_conn/parent.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "./child/child.sim.v"
 
 module PARENT (

diff --git a/tests/io/input/ipad.sim.v b/tests/io/input/ipad.sim.v
index 5288d42..76c88d4 100644
--- a/tests/io/input/ipad.sim.v
+++ b/tests/io/input/ipad.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* CLASS="input" *)
 module IPAD(inpad);
     output wire inpad;

diff --git a/tests/io/output/opad.sim.v b/tests/io/output/opad.sim.v
index 9ce27e1..f82b7f0 100644
--- a/tests/io/output/opad.sim.v
+++ b/tests/io/output/opad.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* CLASS="output" *)
 module OPAD(outpad);
     input  wire outpad;

diff --git a/tests/logicbox/logicbox.sim.v b/tests/logicbox/logicbox.sim.v
index 6ac2b93..b850219 100644
--- a/tests/logicbox/logicbox.sim.v
+++ b/tests/logicbox/logicbox.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* whitebox *)
 module LOGICBOX (I, O);
 	input wire I;

diff --git a/tests/modes/inv.sim.v b/tests/modes/inv.sim.v
index 45fd3df..893673f 100644
--- a/tests/modes/inv.sim.v
+++ b/tests/modes/inv.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "./not/not.sim.v"
 
 (* MODES="PASSTHROUGH;INVERT" *)

diff --git a/tests/modes/not/not.sim.v b/tests/modes/not/not.sim.v
index c4b4d1d..760a2ca 100644
--- a/tests/modes/not/not.sim.v
+++ b/tests/modes/not/not.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* whitebox *)
 module NOT (I, O);
 

diff --git a/tests/multiple_instance/multiple_instance.sim.v b/tests/multiple_instance/multiple_instance.sim.v
index 46536e9..ab3423a 100644
--- a/tests/multiple_instance/multiple_instance.sim.v
+++ b/tests/multiple_instance/multiple_instance.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "../vtr/full-adder/adder.sim.v"
 module MULTIPLE_INSTANCE (a, b, c, d, cin, cout, sum);
 	localparam DATA_WIDTH = 4;

diff --git a/tests/muxes/use_mux.sim.v b/tests/muxes/use_mux.sim.v
index 9ba59b0..5b256fa 100644
--- a/tests/muxes/use_mux.sim.v
+++ b/tests/muxes/use_mux.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "routing/rmux.sim.v"
 `include "../logicbox/logicbox.sim.v"
 module USE_MUX (a, b, c, o1, o2);

diff --git a/tests/net_attr/child/child.sim.v b/tests/net_attr/child/child.sim.v
index e09db94..dc71b17 100644
--- a/tests/net_attr/child/child.sim.v
+++ b/tests/net_attr/child/child.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 module CHILD(
     input  wire I,
     output wire O

diff --git a/tests/net_attr/parent.sim.v b/tests/net_attr/parent.sim.v
index 599456a..84d80bc 100644
--- a/tests/net_attr/parent.sim.v
+++ b/tests/net_attr/parent.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "./child/child.sim.v"
 
 module PARENT(

diff --git a/tests/no_comb/ff.sim.v b/tests/no_comb/ff.sim.v
index bddea78..d5c8507 100644
--- a/tests/no_comb/ff.sim.v
+++ b/tests/no_comb/ff.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* whitebox *)
 module FF(clk, D, S, R, E, Q);
 	input wire clk;

diff --git a/tests/simple_pll/simple_pll.sim.v b/tests/simple_pll/simple_pll.sim.v
index 68ae816..e7e6324 100644
--- a/tests/simple_pll/simple_pll.sim.v
+++ b/tests/simple_pll/simple_pll.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 /* Simple model of a PLL which divides the input block by 64 */
 module SIMPLE_PLL (in_clock, out_clock);
 

diff --git a/tests/test_v2x.py b/tests/test_v2x.py
index 127b9ce..8c3c83c 100644
--- a/tests/test_v2x.py
+++ b/tests/test_v2x.py

@@ -1,4 +1,13 @@
 #!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:	ISC
 
 from pathlib import Path
 import os

diff --git a/tests/vtr/dff/dff.sim.v b/tests/vtr/dff/dff.sim.v
index 3927929..91c1c12 100644
--- a/tests/vtr/dff/dff.sim.v
+++ b/tests/vtr/dff/dff.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* whitebox *)
 module DFF (D, CLK, Q);
 

diff --git a/tests/vtr/full-adder/adder.sim.v b/tests/vtr/full-adder/adder.sim.v
index 2088a77..c07e0e1 100644
--- a/tests/vtr/full-adder/adder.sim.v
+++ b/tests/vtr/full-adder/adder.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* whitebox *)
 module ADDER (
 	a, b, cin,

diff --git a/tests/vtr/lutff-pair/ff/ff.sim.v b/tests/vtr/lutff-pair/ff/ff.sim.v
index 2490547..8eb2141 100644
--- a/tests/vtr/lutff-pair/ff/ff.sim.v
+++ b/tests/vtr/lutff-pair/ff/ff.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* whitebox *)
 module DFF (CLK, D, Q);
 

diff --git a/tests/vtr/lutff-pair/lut/lut4.sim.v b/tests/vtr/lutff-pair/lut/lut4.sim.v
index caa640b..d8b9487 100644
--- a/tests/vtr/lutff-pair/lut/lut4.sim.v
+++ b/tests/vtr/lutff-pair/lut/lut4.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 (* whitebox *)
 module LUT4 (I, O);
 	input wire [3:0] I;

diff --git a/tests/vtr/lutff-pair/pair.sim.v b/tests/vtr/lutff-pair/pair.sim.v
index 750cf65..025bea2 100644
--- a/tests/vtr/lutff-pair/pair.sim.v
+++ b/tests/vtr/lutff-pair/pair.sim.v

@@ -1,3 +1,13 @@
+/*
+ * Copyright (C) 2020  The SymbiFlow Authors.
+ *
+ * Use of this source code is governed by a ISC-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/ISC
+ *
+ * SPDX-License-Identifier:	ISC
+ */
+
 `include "lut/lut4.sim.v"
 `include "ff/ff.sim.v"
 `include "omux/omux.sim.v"

diff --git a/v2x/__main__.py b/v2x/__main__.py
index 38ba16d..0a33dce 100644
--- a/v2x/__main__.py
+++ b/v2x/__main__.py

@@ -1,4 +1,13 @@
 #!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:	ISC
 
 from . import vlog_to_pbtype
 from . import vlog_to_model

diff --git a/v2x/lib/argparse_extra.py b/v2x/lib/argparse_extra.py
index 9be1116..4dc1ab3 100644
--- a/v2x/lib/argparse_extra.py
+++ b/v2x/lib/argparse_extra.py

@@ -1,4 +1,14 @@
 #!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:	ISC
+
 import argparse
 
 

diff --git a/v2x/lib/asserts.py b/v2x/lib/asserts.py
index e341f32..8f5b4ad 100644
--- a/v2x/lib/asserts.py
+++ b/v2x/lib/asserts.py

@@ -1,4 +1,15 @@
 #!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:	ISC
+
+
 def __safe_call(f, a):
     """Call a function and capture all exceptions."""
     try:

diff --git a/v2x/lib/mux.py b/v2x/lib/mux.py
index 700d02b..68b954a 100644
--- a/v2x/lib/mux.py
+++ b/v2x/lib/mux.py

@@ -1,4 +1,14 @@
 #!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:	ISC
+
 import lxml.etree as ET
 from enum import Enum
 

diff --git a/v2x/mux_gen.py b/v2x/mux_gen.py
index f24950f..c16ea80 100755
--- a/v2x/mux_gen.py
+++ b/v2x/mux_gen.py

@@ -1,4 +1,14 @@
 #!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:	ISC
+
 """
 Generate MUX.
 

diff --git a/v2x/vlog_to_model.py b/v2x/vlog_to_model.py
index 3477de1..f234925 100755
--- a/v2x/vlog_to_model.py
+++ b/v2x/vlog_to_model.py

@@ -1,4 +1,14 @@
 #!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:	ISC
+
 """
 Convert a Verilog simulation model to a VPR `model.xml`
 

diff --git a/v2x/vlog_to_pbtype.py b/v2x/vlog_to_pbtype.py
index 7146992..74fa32a 100755
--- a/v2x/vlog_to_pbtype.py
+++ b/v2x/vlog_to_pbtype.py

@@ -1,4 +1,14 @@
 #!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:	ISC
+
 """\
 Convert a Verilog simulation model to a VPR `pb_type.xml`
 

diff --git a/v2x/xmlinc/xmlinc.py b/v2x/xmlinc/xmlinc.py
index b611534..b519953 100644
--- a/v2x/xmlinc/xmlinc.py
+++ b/v2x/xmlinc/xmlinc.py

@@ -1,4 +1,14 @@
 #!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:	ISC
+
 import lxml.etree as ET
 import os
 

diff --git a/v2x/yosys/json.py b/v2x/yosys/json.py
index 93a32da..b17ea1c 100755
--- a/v2x/yosys/json.py
+++ b/v2x/yosys/json.py

@@ -1,4 +1,14 @@
 #!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:	ISC
+
 """
 This is intended to provide a range of helper functions around the output of
 Yosys' `write_json`. Depending on the tasks, this may need to be flattened

diff --git a/v2x/yosys/run.py b/v2x/yosys/run.py
index ef2627e..2852133 100755
--- a/v2x/yosys/run.py
+++ b/v2x/yosys/run.py

@@ -1,4 +1,14 @@
 #!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:	ISC
+
 import json
 import os
 import re

diff --git a/v2x/yosys/utils.py b/v2x/yosys/utils.py
index f6c3597..1afd475 100644
--- a/v2x/yosys/utils.py
+++ b/v2x/yosys/utils.py

@@ -1,4 +1,14 @@
 #!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2020  The SymbiFlow Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier:	ISC
+
 import re
 
 CLOCK_NAME_REGEX = re.compile(r"[a-z_]*clk[a-z0-9]*$")