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foss-fpga-tools/third_party/yosys/5603595e5c0efd2afc9ba810e6e5992e5d81d44c^!/.
commit
5603595e5c0efd2afc9ba810e6e5992e5d81d44c
[log]
author
Miodrag Milanovic <mmicko@gmail.com>
Fri Oct 18 12:19:59 2019 +0200
committer
Miodrag Milanovic <mmicko@gmail.com>
Fri Oct 18 12:19:59 2019 +0200
tree
dcf99c611410e055a7ea71c970938ed6ee50a3c6
parent
ab98f2dccf52a1bba396fe313ea0670603dc45ca [diff] 
Share common tests

diff --git a/tests/arch/anlogic/add_sub.v b/tests/arch/anlogic/add_sub.v
deleted file mode 100644
index 177c32e..0000000
--- a/tests/arch/anlogic/add_sub.v
+++ /dev/null

@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule

diff --git a/tests/arch/anlogic/add_sub.ys b/tests/arch/anlogic/add_sub.ys
index b8b67cc..5396ce7 100644
--- a/tests/arch/anlogic/add_sub.ys
+++ b/tests/arch/anlogic/add_sub.ys

@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check

diff --git a/tests/arch/anlogic/counter.v b/tests/arch/anlogic/counter.v
deleted file mode 100644
index 52852f8..0000000
--- a/tests/arch/anlogic/counter.v
+++ /dev/null

@@ -1,17 +0,0 @@
-module top    (

-out,

-clk,

-reset

-);

-    output [7:0] out;

-    input clk, reset;

-    reg [7:0] out;

-

-    always @(posedge clk, posedge reset)

-		if (reset) begin

-			out <= 8'b0 ;

-		end else

-			out <= out + 1;

-

-

-endmodule


diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys
index 036fdba..d363ec2 100644
--- a/tests/arch/anlogic/counter.ys
+++ b/tests/arch/anlogic/counter.ys

@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten

diff --git a/tests/arch/anlogic/dffs.v b/tests/arch/anlogic/dffs.v
deleted file mode 100644
index 3418787..0000000
--- a/tests/arch/anlogic/dffs.v
+++ /dev/null

@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule

diff --git a/tests/arch/anlogic/dffs.ys b/tests/arch/anlogic/dffs.ys
index 9cbe5fc..d3281ab 100644
--- a/tests/arch/anlogic/dffs.ys
+++ b/tests/arch/anlogic/dffs.ys

@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff

diff --git a/tests/arch/anlogic/fsm.v b/tests/arch/anlogic/fsm.v
deleted file mode 100644
index 368fbaa..0000000
--- a/tests/arch/anlogic/fsm.v
+++ /dev/null

@@ -1,55 +0,0 @@
- module fsm (

- clock,

- reset,

- req_0,

- req_1,

- gnt_0,

- gnt_1

- );

- input   clock,reset,req_0,req_1;

- output  gnt_0,gnt_1;

- wire    clock,reset,req_0,req_1;

- reg     gnt_0,gnt_1;

-

- parameter SIZE = 3           ;

- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;

-

- reg [SIZE-1:0] state;

- reg [SIZE-1:0] next_state;

-

- always @ (posedge clock)

- begin : FSM

- if (reset == 1'b1) begin

-   state <=  #1  IDLE;

-   gnt_0 <= 0;

-   gnt_1 <= 0;

- end else

-  case(state)

-    IDLE : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-                 gnt_0 <= 1;

-               end else if (req_1 == 1'b1) begin

-                 gnt_1 <= 1;

-                 state <=  #1  GNT0;

-               end else begin

-                 state <=  #1  IDLE;

-               end

-    GNT0 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-               end else begin

-                 gnt_0 <= 0;

-                 state <=  #1  IDLE;

-               end

-    GNT1 : if (req_1 == 1'b1) begin

-                 state <=  #1  GNT2;

-				 gnt_1 <= req_0;

-               end

-    GNT2 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT1;

-				 gnt_1 <= req_1;

-               end

-    default : state <=  #1  IDLE;

- endcase

- end

-

-endmodule


diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys
index 452ef92..f45951b 100644
--- a/tests/arch/anlogic/fsm.ys
+++ b/tests/arch/anlogic/fsm.ys

@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 #flatten

diff --git a/tests/arch/anlogic/latches.v b/tests/arch/anlogic/latches.v
deleted file mode 100644
index adb5d53..0000000
--- a/tests/arch/anlogic/latches.v
+++ /dev/null

@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule

diff --git a/tests/arch/anlogic/latches.ys b/tests/arch/anlogic/latches.ys
index c00c7a2..8d66f77 100644
--- a/tests/arch/anlogic/latches.ys
+++ b/tests/arch/anlogic/latches.ys

@@ -1,4 +1,4 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp

diff --git a/tests/arch/anlogic/logic.ys b/tests/arch/anlogic/logic.ys
new file mode 100644
index 0000000..125ee5d
--- /dev/null
+++ b/tests/arch/anlogic/logic.ys

@@ -0,0 +1,11 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:AL_MAP_LUT1
+select -assert-count 6 t:AL_MAP_LUT2
+select -assert-count 2 t:AL_MAP_LUT4
+select -assert-none t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT4 %% t:* %D

diff --git a/tests/arch/anlogic/mux.v b/tests/arch/anlogic/mux.v
deleted file mode 100644
index 27bc0bf..0000000
--- a/tests/arch/anlogic/mux.v
+++ /dev/null

@@ -1,65 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule

diff --git a/tests/arch/anlogic/mux.ys b/tests/arch/anlogic/mux.ys
index 64ed2a2..3d5fe7c 100644
--- a/tests/arch/anlogic/mux.ys
+++ b/tests/arch/anlogic/mux.ys

@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2

diff --git a/tests/arch/anlogic/shifter.v b/tests/arch/anlogic/shifter.v
deleted file mode 100644
index 04ae49d..0000000
--- a/tests/arch/anlogic/shifter.v
+++ /dev/null

@@ -1,16 +0,0 @@
-module top    (

-out,

-clk,

-in

-);

-    output [7:0] out;

-    input signed clk, in;

-    reg signed [7:0] out = 0;

-

-    always @(posedge clk)

-	begin

-		out    <= out >> 1;

-		out[7] <= in;

-	end

-

-endmodule


diff --git a/tests/arch/anlogic/shifter.ys b/tests/arch/anlogic/shifter.ys
index 5eaed30..12df44b 100644
--- a/tests/arch/anlogic/shifter.ys
+++ b/tests/arch/anlogic/shifter.ys

@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten

diff --git a/tests/arch/anlogic/tribuf.v b/tests/arch/anlogic/tribuf.v
deleted file mode 100644
index 90dd314..0000000
--- a/tests/arch/anlogic/tribuf.v
+++ /dev/null

@@ -1,8 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output o;
-
-	assign o = en ? i : 1'bz;
-
-endmodule

diff --git a/tests/arch/anlogic/tribuf.ys b/tests/arch/anlogic/tribuf.ys
index 0eb1338..eaa0737 100644
--- a/tests/arch/anlogic/tribuf.ys
+++ b/tests/arch/anlogic/tribuf.ys

@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 flatten

diff --git a/tests/arch/ecp5/add_sub.v b/tests/arch/common/add_sub.v
similarity index 100%
rename from tests/arch/ecp5/add_sub.v
rename to tests/arch/common/add_sub.v

diff --git a/tests/arch/ecp5/adffs.v b/tests/arch/common/adffs.v
similarity index 100%
rename from tests/arch/ecp5/adffs.v
rename to tests/arch/common/adffs.v

diff --git a/tests/arch/ecp5/counter.v b/tests/arch/common/counter.v
similarity index 100%
rename from tests/arch/ecp5/counter.v
rename to tests/arch/common/counter.v

diff --git a/tests/arch/ecp5/dffs.v b/tests/arch/common/dffs.v
similarity index 100%
rename from tests/arch/ecp5/dffs.v
rename to tests/arch/common/dffs.v

diff --git a/tests/arch/ecp5/fsm.v b/tests/arch/common/fsm.v
similarity index 100%
rename from tests/arch/ecp5/fsm.v
rename to tests/arch/common/fsm.v

diff --git a/tests/arch/ecp5/latches.v b/tests/arch/common/latches.v
similarity index 100%
rename from tests/arch/ecp5/latches.v
rename to tests/arch/common/latches.v

diff --git a/tests/arch/ecp5/logic.v b/tests/arch/common/logic.v
similarity index 100%
rename from tests/arch/ecp5/logic.v
rename to tests/arch/common/logic.v

diff --git a/tests/arch/ecp5/mul.v b/tests/arch/common/mul.v
similarity index 100%
rename from tests/arch/ecp5/mul.v
rename to tests/arch/common/mul.v

diff --git a/tests/arch/efinix/mux.v b/tests/arch/common/mux.v
similarity index 100%
rename from tests/arch/efinix/mux.v
rename to tests/arch/common/mux.v

diff --git a/tests/arch/ecp5/shifter.v b/tests/arch/common/shifter.v
similarity index 100%
rename from tests/arch/ecp5/shifter.v
rename to tests/arch/common/shifter.v

diff --git a/tests/arch/efinix/tribuf.v b/tests/arch/common/tribuf.v
similarity index 100%
rename from tests/arch/efinix/tribuf.v
rename to tests/arch/common/tribuf.v

diff --git a/tests/arch/ecp5/add_sub.ys b/tests/arch/ecp5/add_sub.ys
index ee72d73..d85ce79 100644
--- a/tests/arch/ecp5/add_sub.ys
+++ b/tests/arch/ecp5/add_sub.ys

@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check

diff --git a/tests/arch/ecp5/adffs.ys b/tests/arch/ecp5/adffs.ys
index c6780e5..01605df 100644
--- a/tests/arch/ecp5/adffs.ys
+++ b/tests/arch/ecp5/adffs.ys

@@ -1,4 +1,4 @@
-read_verilog adffs.v
+read_verilog ../common/adffs.v
 design -save read
 
 hierarchy -top adff

diff --git a/tests/arch/ecp5/counter.ys b/tests/arch/ecp5/counter.ys
index 8ef7077..f9f60fb 100644
--- a/tests/arch/ecp5/counter.ys
+++ b/tests/arch/ecp5/counter.ys

@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten

diff --git a/tests/arch/ecp5/dffs.ys b/tests/arch/ecp5/dffs.ys
index a4f45d2..be97972 100644
--- a/tests/arch/ecp5/dffs.ys
+++ b/tests/arch/ecp5/dffs.ys

@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff

diff --git a/tests/arch/ecp5/fsm.ys b/tests/arch/ecp5/fsm.ys
index ded91e5..f834a4c 100644
--- a/tests/arch/ecp5/fsm.ys
+++ b/tests/arch/ecp5/fsm.ys

@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 flatten

diff --git a/tests/arch/ecp5/latches.ys b/tests/arch/ecp5/latches.ys
index fc15a69..3d011d7 100644
--- a/tests/arch/ecp5/latches.ys
+++ b/tests/arch/ecp5/latches.ys

@@ -1,5 +1,4 @@
-
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp

diff --git a/tests/arch/ecp5/logic.ys b/tests/arch/ecp5/logic.ys
index 4f113a1..3298b19 100644
--- a/tests/arch/ecp5/logic.ys
+++ b/tests/arch/ecp5/logic.ys

@@ -1,4 +1,4 @@
-read_verilog logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check

diff --git a/tests/arch/ecp5/mul.ys b/tests/arch/ecp5/mul.ys
index 0a91f89..2105be5 100644
--- a/tests/arch/ecp5/mul.ys
+++ b/tests/arch/ecp5/mul.ys

@@ -1,4 +1,4 @@
-read_verilog mul.v
+read_verilog ../common/mul.v
 hierarchy -top top
 proc
 # Blocked by issue #1358 (Missing ECP5 simulation models)

diff --git a/tests/arch/ecp5/mux.v b/tests/arch/ecp5/mux.v
deleted file mode 100644
index 782424a..0000000
--- a/tests/arch/ecp5/mux.v
+++ /dev/null

@@ -1,66 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
-

diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys
index 8cfbd54..92463aa 100644
--- a/tests/arch/ecp5/mux.ys
+++ b/tests/arch/ecp5/mux.ys

@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2

diff --git a/tests/arch/ecp5/shifter.ys b/tests/arch/ecp5/shifter.ys
index e1901e1..3f0079f 100644
--- a/tests/arch/ecp5/shifter.ys
+++ b/tests/arch/ecp5/shifter.ys

@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten

diff --git a/tests/arch/ecp5/tribuf.v b/tests/arch/ecp5/tribuf.v
deleted file mode 100644
index 90dd314..0000000
--- a/tests/arch/ecp5/tribuf.v
+++ /dev/null

@@ -1,8 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output o;
-
-	assign o = en ? i : 1'bz;
-
-endmodule

diff --git a/tests/arch/ecp5/tribuf.ys b/tests/arch/ecp5/tribuf.ys
index a6e9c95..0118705 100644
--- a/tests/arch/ecp5/tribuf.ys
+++ b/tests/arch/ecp5/tribuf.ys

@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 flatten

diff --git a/tests/arch/efinix/add_sub.v b/tests/arch/efinix/add_sub.v
deleted file mode 100644
index 177c32e..0000000
--- a/tests/arch/efinix/add_sub.v
+++ /dev/null

@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule

diff --git a/tests/arch/efinix/add_sub.ys b/tests/arch/efinix/add_sub.ys
index 8bd28c6..20523c0 100644
--- a/tests/arch/efinix/add_sub.ys
+++ b/tests/arch/efinix/add_sub.ys

@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check

diff --git a/tests/arch/efinix/adffs.v b/tests/arch/efinix/adffs.v
deleted file mode 100644
index 223b52d..0000000
--- a/tests/arch/efinix/adffs.v
+++ /dev/null

@@ -1,47 +0,0 @@
-module adff
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module adffn
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module dffs
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( negedge clk )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule

diff --git a/tests/arch/efinix/adffs.ys b/tests/arch/efinix/adffs.ys
index 1069c6c..49dc7f2 100644
--- a/tests/arch/efinix/adffs.ys
+++ b/tests/arch/efinix/adffs.ys

@@ -1,4 +1,4 @@
-read_verilog adffs.v
+read_verilog ../common/adffs.v
 design -save read
 
 hierarchy -top adff

diff --git a/tests/arch/efinix/counter.v b/tests/arch/efinix/counter.v
deleted file mode 100644
index 52852f8..0000000
--- a/tests/arch/efinix/counter.v
+++ /dev/null

@@ -1,17 +0,0 @@
-module top    (

-out,

-clk,

-reset

-);

-    output [7:0] out;

-    input clk, reset;

-    reg [7:0] out;

-

-    always @(posedge clk, posedge reset)

-		if (reset) begin

-			out <= 8'b0 ;

-		end else

-			out <= out + 1;

-

-

-endmodule


diff --git a/tests/arch/efinix/counter.ys b/tests/arch/efinix/counter.ys
index 82e61d3..d20b8ae 100644
--- a/tests/arch/efinix/counter.ys
+++ b/tests/arch/efinix/counter.ys

@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten

diff --git a/tests/arch/efinix/dffs.v b/tests/arch/efinix/dffs.v
deleted file mode 100644
index 3418787..0000000
--- a/tests/arch/efinix/dffs.v
+++ /dev/null

@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule

diff --git a/tests/arch/efinix/dffs.ys b/tests/arch/efinix/dffs.ys
index cdd2882..af787ab 100644
--- a/tests/arch/efinix/dffs.ys
+++ b/tests/arch/efinix/dffs.ys

@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff

diff --git a/tests/arch/efinix/fsm.v b/tests/arch/efinix/fsm.v
deleted file mode 100644
index 368fbaa..0000000
--- a/tests/arch/efinix/fsm.v
+++ /dev/null

@@ -1,55 +0,0 @@
- module fsm (

- clock,

- reset,

- req_0,

- req_1,

- gnt_0,

- gnt_1

- );

- input   clock,reset,req_0,req_1;

- output  gnt_0,gnt_1;

- wire    clock,reset,req_0,req_1;

- reg     gnt_0,gnt_1;

-

- parameter SIZE = 3           ;

- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;

-

- reg [SIZE-1:0] state;

- reg [SIZE-1:0] next_state;

-

- always @ (posedge clock)

- begin : FSM

- if (reset == 1'b1) begin

-   state <=  #1  IDLE;

-   gnt_0 <= 0;

-   gnt_1 <= 0;

- end else

-  case(state)

-    IDLE : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-                 gnt_0 <= 1;

-               end else if (req_1 == 1'b1) begin

-                 gnt_1 <= 1;

-                 state <=  #1  GNT0;

-               end else begin

-                 state <=  #1  IDLE;

-               end

-    GNT0 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-               end else begin

-                 gnt_0 <= 0;

-                 state <=  #1  IDLE;

-               end

-    GNT1 : if (req_1 == 1'b1) begin

-                 state <=  #1  GNT2;

-				 gnt_1 <= req_0;

-               end

-    GNT2 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT1;

-				 gnt_1 <= req_1;

-               end

-    default : state <=  #1  IDLE;

- endcase

- end

-

-endmodule


diff --git a/tests/arch/efinix/fsm.ys b/tests/arch/efinix/fsm.ys
index 2ec7521..a8ba70f 100644
--- a/tests/arch/efinix/fsm.ys
+++ b/tests/arch/efinix/fsm.ys

@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 flatten

diff --git a/tests/arch/efinix/latches.v b/tests/arch/efinix/latches.v
deleted file mode 100644
index adb5d53..0000000
--- a/tests/arch/efinix/latches.v
+++ /dev/null

@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule

diff --git a/tests/arch/efinix/latches.ys b/tests/arch/efinix/latches.ys
index 899d024..1b1c000 100644
--- a/tests/arch/efinix/latches.ys
+++ b/tests/arch/efinix/latches.ys

@@ -1,4 +1,4 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp

diff --git a/tests/arch/efinix/logic.v b/tests/arch/efinix/logic.v
deleted file mode 100644
index e5343ca..0000000
--- a/tests/arch/efinix/logic.v
+++ /dev/null

@@ -1,18 +0,0 @@
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
-endmodule

diff --git a/tests/arch/efinix/logic.ys b/tests/arch/efinix/logic.ys
index fdedb33..76e98e0 100644
--- a/tests/arch/efinix/logic.ys
+++ b/tests/arch/efinix/logic.ys

@@ -1,4 +1,4 @@
-read_verilog logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check

diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys
index 71a9681..b46f641 100644
--- a/tests/arch/efinix/mux.ys
+++ b/tests/arch/efinix/mux.ys

@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2

diff --git a/tests/arch/efinix/shifter.v b/tests/arch/efinix/shifter.v
deleted file mode 100644
index ce2c81d..0000000
--- a/tests/arch/efinix/shifter.v
+++ /dev/null

@@ -1,16 +0,0 @@
-module top    (

-out,

-clk,

-in

-);

-    output [7:0] out;

-    input signed clk, in;

-    reg signed [7:0] out = 0;

-

-    always @(posedge clk)

-	begin

-		out    <= out << 1;

-		out[7] <= in;

-	end

-

-endmodule


diff --git a/tests/arch/efinix/shifter.ys b/tests/arch/efinix/shifter.ys
index 1a6b556..54f7116 100644
--- a/tests/arch/efinix/shifter.ys
+++ b/tests/arch/efinix/shifter.ys

@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten

diff --git a/tests/arch/efinix/tribuf.ys b/tests/arch/efinix/tribuf.ys
index 2e2ab9e..47904f2 100644
--- a/tests/arch/efinix/tribuf.ys
+++ b/tests/arch/efinix/tribuf.ys

@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 tribuf

diff --git a/tests/arch/ice40/add_sub.v b/tests/arch/ice40/add_sub.v
deleted file mode 100644
index 177c32e..0000000
--- a/tests/arch/ice40/add_sub.v
+++ /dev/null

@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule

diff --git a/tests/arch/ice40/add_sub.ys b/tests/arch/ice40/add_sub.ys
index 4a998d9..578ec08 100644
--- a/tests/arch/ice40/add_sub.ys
+++ b/tests/arch/ice40/add_sub.ys

@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

diff --git a/tests/arch/ice40/adffs.v b/tests/arch/ice40/adffs.v
deleted file mode 100644
index 09dc360..0000000
--- a/tests/arch/ice40/adffs.v
+++ /dev/null

@@ -1,87 +0,0 @@
-module adff
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module adffn
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module dffs
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge pre )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( negedge clk, negedge pre )
-		if ( !pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2,b3
-);
-
-dffs u_dffs (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b )
-    );
-
-ndffnr u_ndffnr (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b1 )
-    );
-
-adff u_adff (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b2 )
-    );
-
-adffn u_adffn (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b3 )
-    );
-
-endmodule

diff --git a/tests/arch/ice40/adffs.ys b/tests/arch/ice40/adffs.ys
index 548060b..e5dbabb 100644
--- a/tests/arch/ice40/adffs.ys
+++ b/tests/arch/ice40/adffs.ys

@@ -1,11 +1,39 @@
-read_verilog adffs.v
+read_verilog ../common/adffs.v
+design -save read
+
+hierarchy -top adff
 proc
-flatten
-equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFFNS
-select -assert-count 2 t:SB_DFFR
-select -assert-count 1 t:SB_DFFS
-select -assert-count 2 t:SB_LUT4
-select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFR
+select -assert-none t:SB_DFFR %% t:* %D
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFR
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_DFFR t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFSS
+select -assert-none t:SB_DFFSS %% t:* %D
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFNSR
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_DFFNSR t:SB_LUT4 %% t:* %D

diff --git a/tests/arch/ice40/counter.v b/tests/arch/ice40/counter.v
deleted file mode 100644
index 52852f8..0000000
--- a/tests/arch/ice40/counter.v
+++ /dev/null

@@ -1,17 +0,0 @@
-module top    (

-out,

-clk,

-reset

-);

-    output [7:0] out;

-    input clk, reset;

-    reg [7:0] out;

-

-    always @(posedge clk, posedge reset)

-		if (reset) begin

-			out <= 8'b0 ;

-		end else

-			out <= out + 1;

-

-

-endmodule


diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys
index c65c216..f112eb9 100644
--- a/tests/arch/ice40/counter.ys
+++ b/tests/arch/ice40/counter.ys

@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten

diff --git a/tests/arch/ice40/dffs.v b/tests/arch/ice40/dffs.v
deleted file mode 100644
index d97840c..0000000
--- a/tests/arch/ice40/dffs.v
+++ /dev/null

@@ -1,37 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule
-
-module top (
-input clk,
-input en,
-input a,
-output b,b1,
-);
-
-dff u_dff (
-        .clk (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-dffe u_ndffe (
-        .clk (clk ),
-        .en (en),
-        .d (a ),
-        .q (b1 )
-    );
-
-endmodule

diff --git a/tests/arch/ice40/dffs.ys b/tests/arch/ice40/dffs.ys
index ee7f884..b28a5a9 100644
--- a/tests/arch/ice40/dffs.ys
+++ b/tests/arch/ice40/dffs.ys

@@ -1,10 +1,19 @@
-read_verilog dffs.v
-hierarchy -top top
+read_verilog ../common/dffs.v
+design -save read
+
+hierarchy -top dff
 proc
-flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFF
+select -assert-none t:SB_DFF %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFFE
-select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D
+select -assert-none t:SB_DFFE %% t:* %D
\ No newline at end of file

diff --git a/tests/arch/ice40/fsm.v b/tests/arch/ice40/fsm.v
deleted file mode 100644
index 0605bd1..0000000
--- a/tests/arch/ice40/fsm.v
+++ /dev/null

@@ -1,73 +0,0 @@
- module fsm (

- clock,

- reset,

- req_0,

- req_1,

- gnt_0,

- gnt_1

- );

- input   clock,reset,req_0,req_1;

- output  gnt_0,gnt_1;

- wire    clock,reset,req_0,req_1;

- reg     gnt_0,gnt_1;

-

- parameter SIZE = 3           ;

- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;

-

- reg [SIZE-1:0] state;

- reg [SIZE-1:0] next_state;

-

- always @ (posedge clock)

- begin : FSM

- if (reset == 1'b1) begin

-   state <=  #1  IDLE;

-   gnt_0 <= 0;

-   gnt_1 <= 0;

- end else

-  case(state)

-    IDLE : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-                 gnt_0 <= 1;

-               end else if (req_1 == 1'b1) begin

-                 gnt_1 <= 1;

-                 state <=  #1  GNT0;

-               end else begin

-                 state <=  #1  IDLE;

-               end

-    GNT0 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-               end else begin

-                 gnt_0 <= 0;

-                 state <=  #1  IDLE;

-               end

-    GNT1 : if (req_1 == 1'b1) begin

-                 state <=  #1  GNT2;

-				 gnt_1 <= req_0;

-               end

-    GNT2 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT1;

-				 gnt_1 <= req_1;

-               end

-    default : state <=  #1  IDLE;

- endcase

- end

-

- endmodule

-

- module top (

-input clk,

-input rst,

-input a,

-input b,

-output g0,

-output g1

-);

-

-fsm u_fsm ( .clock(clk),

-            .reset(rst),

-            .req_0(a),

-            .req_1(b),

-            .gnt_0(g0),

-            .gnt_1(g1));

-

-endmodule


diff --git a/tests/arch/ice40/fsm.ys b/tests/arch/ice40/fsm.ys
index 4cc8629..5aacc6c 100644
--- a/tests/arch/ice40/fsm.ys
+++ b/tests/arch/ice40/fsm.ys

@@ -1,10 +1,10 @@
-read_verilog fsm.v
-hierarchy -top top
+read_verilog ../common/fsm.v
+hierarchy -top fsm
 proc
 flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 2 t:SB_DFFESR
 select -assert-count 2 t:SB_DFFSR

diff --git a/tests/arch/ice40/latches.v b/tests/arch/ice40/latches.v
deleted file mode 100644
index 9dc43e4..0000000
--- a/tests/arch/ice40/latches.v
+++ /dev/null

@@ -1,58 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule
-
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2
-);
-
-
-latchp u_latchp (
-        .en (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-
-latchn u_latchn (
-        .en (clk ),
-        .d (a ),
-        .q (b1 )
-    );
-
-
-latchsr u_latchsr (
-        .en (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b2 )
-    );
-
-endmodule

diff --git a/tests/arch/ice40/latches.ys b/tests/arch/ice40/latches.ys
index 708734e..b06dd63 100644
--- a/tests/arch/ice40/latches.ys
+++ b/tests/arch/ice40/latches.ys

@@ -1,12 +1,33 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
+design -save read
 
+hierarchy -top latchp
 proc
-flatten
 # Can't run any sort of equivalence check because latches are blown to LUTs
-#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-
-#design -load preopt
 synth_ice40
-cd top
-select -assert-count 4 t:SB_LUT4
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
+
+design -load read
+hierarchy -top latchn
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_ice40
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
+
+design -load read
+hierarchy -top latchsr
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_ice40
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 2 t:SB_LUT4
+
 select -assert-none t:SB_LUT4 %% t:* %D

diff --git a/tests/arch/ice40/logic.v b/tests/arch/ice40/logic.v
deleted file mode 100644
index e5343ca..0000000
--- a/tests/arch/ice40/logic.v
+++ /dev/null

@@ -1,18 +0,0 @@
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
-endmodule

diff --git a/tests/arch/ice40/logic.ys b/tests/arch/ice40/logic.ys
index fc5e5b1..7432f5b 100644
--- a/tests/arch/ice40/logic.ys
+++ b/tests/arch/ice40/logic.ys

@@ -1,4 +1,4 @@
-read_verilog logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

diff --git a/tests/arch/ice40/mul.v b/tests/arch/ice40/mul.v
deleted file mode 100644
index d5b48b1..0000000
--- a/tests/arch/ice40/mul.v
+++ /dev/null

@@ -1,11 +0,0 @@
-module top
-(
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A =  x * y;
-
-endmodule

diff --git a/tests/arch/ice40/mul.ys b/tests/arch/ice40/mul.ys
index 8a0822a..9891b77 100644
--- a/tests/arch/ice40/mul.ys
+++ b/tests/arch/ice40/mul.ys

@@ -1,4 +1,4 @@
-read_verilog mul.v
+read_verilog ../common/mul.v
 hierarchy -top top
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

diff --git a/tests/arch/ice40/mux.v b/tests/arch/ice40/mux.v
deleted file mode 100644
index 0814b73..0000000
--- a/tests/arch/ice40/mux.v
+++ /dev/null

@@ -1,100 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
-
-
-module top (
-input [3:0] S,
-input [15:0] D,
-output M2,M4,M8,M16
-);
-
-mux2 u_mux2 (
-        .S (S[0]),
-        .A (D[0]),
-        .B (D[1]),
-        .Y (M2)
-    );
-
-
-mux4 u_mux4 (
-        .S (S[1:0]),
-        .D (D[3:0]),
-        .Y (M4)
-    );
-
-mux8 u_mux8 (
-        .S (S[2:0]),
-        .D (D[7:0]),
-        .Y (M8)
-    );
-
-mux16 u_mux16 (
-        .S (S[3:0]),
-        .D (D[15:0]),
-        .Y (M16)
-    );
-
-endmodule

diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys
index 182b494..9982239 100644
--- a/tests/arch/ice40/mux.ys
+++ b/tests/arch/ice40/mux.ys

@@ -1,8 +1,40 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
+design -save read
+
+hierarchy -top mux2
 proc
-flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 19 t:SB_LUT4
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 2 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 5 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 11 t:SB_LUT4
+
 select -assert-none t:SB_LUT4 %% t:* %D

diff --git a/tests/arch/ice40/shifter.v b/tests/arch/ice40/shifter.v
deleted file mode 100644
index c556325..0000000
--- a/tests/arch/ice40/shifter.v
+++ /dev/null

@@ -1,22 +0,0 @@
-module top    (

-out,

-clk,

-in

-);

-    output [7:0] out;

-    input signed clk, in;

-    reg signed [7:0] out = 0;

-

-    always @(posedge clk)

-	begin

-`ifndef BUG

-		out    <= out >> 1;

-		out[7] <= in;

-`else

-

-		out    <= out << 1;

-		out[7] <= in;

-`endif

-	end

-

-endmodule


diff --git a/tests/arch/ice40/shifter.ys b/tests/arch/ice40/shifter.ys
index 47d95d2..08ea64f 100644
--- a/tests/arch/ice40/shifter.ys
+++ b/tests/arch/ice40/shifter.ys

@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten

diff --git a/tests/arch/ice40/tribuf.v b/tests/arch/ice40/tribuf.v
deleted file mode 100644
index 870a025..0000000
--- a/tests/arch/ice40/tribuf.v
+++ /dev/null

@@ -1,23 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output o;
-
-	assign o = en ? i : 1'bz;
-
-endmodule
-
-
-module top (
-input en,
-input a,
-output b
-);
-
-tristate u_tri (
-        .en (en ),
-        .i (a ),
-        .o (b )
-    );
-
-endmodule

diff --git a/tests/arch/ice40/tribuf.ys b/tests/arch/ice40/tribuf.ys
index d1e1b31..10cded9 100644
--- a/tests/arch/ice40/tribuf.ys
+++ b/tests/arch/ice40/tribuf.ys

@@ -1,9 +1,11 @@
-read_verilog tribuf.v
-hierarchy -top top
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
 proc
+tribuf
 flatten
+synth
 equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd tristate # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D

diff --git a/tests/arch/xilinx/add_sub.v b/tests/arch/xilinx/add_sub.v
deleted file mode 100644
index 177c32e..0000000
--- a/tests/arch/xilinx/add_sub.v
+++ /dev/null

@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule

diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys
index f06e7fa..9dbddce 100644
--- a/tests/arch/xilinx/add_sub.ys
+++ b/tests/arch/xilinx/add_sub.ys

@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check

diff --git a/tests/arch/xilinx/adffs.v b/tests/arch/xilinx/adffs.v
deleted file mode 100644
index 223b52d..0000000
--- a/tests/arch/xilinx/adffs.v
+++ /dev/null

@@ -1,47 +0,0 @@
-module adff
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module adffn
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module dffs
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( negedge clk )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule

diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys
index 1923b98..12c3441 100644
--- a/tests/arch/xilinx/adffs.ys
+++ b/tests/arch/xilinx/adffs.ys

@@ -1,4 +1,4 @@
-read_verilog adffs.v
+read_verilog ../common/adffs.v
 design -save read
 
 hierarchy -top adff

diff --git a/tests/arch/xilinx/counter.v b/tests/arch/xilinx/counter.v
deleted file mode 100644
index 52852f8..0000000
--- a/tests/arch/xilinx/counter.v
+++ /dev/null

@@ -1,17 +0,0 @@
-module top    (

-out,

-clk,

-reset

-);

-    output [7:0] out;

-    input clk, reset;

-    reg [7:0] out;

-

-    always @(posedge clk, posedge reset)

-		if (reset) begin

-			out <= 8'b0 ;

-		end else

-			out <= out + 1;

-

-

-endmodule


diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys
index 4595416..57b645d 100644
--- a/tests/arch/xilinx/counter.ys
+++ b/tests/arch/xilinx/counter.ys

@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten

diff --git a/tests/arch/xilinx/dffs.v b/tests/arch/xilinx/dffs.v
deleted file mode 100644
index 3418787..0000000
--- a/tests/arch/xilinx/dffs.v
+++ /dev/null

@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule

diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys
index f1716da..0bba485 100644
--- a/tests/arch/xilinx/dffs.ys
+++ b/tests/arch/xilinx/dffs.ys

@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff

diff --git a/tests/arch/xilinx/fsm.v b/tests/arch/xilinx/fsm.v
deleted file mode 100644
index 368fbaa..0000000
--- a/tests/arch/xilinx/fsm.v
+++ /dev/null

@@ -1,55 +0,0 @@
- module fsm (

- clock,

- reset,

- req_0,

- req_1,

- gnt_0,

- gnt_1

- );

- input   clock,reset,req_0,req_1;

- output  gnt_0,gnt_1;

- wire    clock,reset,req_0,req_1;

- reg     gnt_0,gnt_1;

-

- parameter SIZE = 3           ;

- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;

-

- reg [SIZE-1:0] state;

- reg [SIZE-1:0] next_state;

-

- always @ (posedge clock)

- begin : FSM

- if (reset == 1'b1) begin

-   state <=  #1  IDLE;

-   gnt_0 <= 0;

-   gnt_1 <= 0;

- end else

-  case(state)

-    IDLE : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-                 gnt_0 <= 1;

-               end else if (req_1 == 1'b1) begin

-                 gnt_1 <= 1;

-                 state <=  #1  GNT0;

-               end else begin

-                 state <=  #1  IDLE;

-               end

-    GNT0 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-               end else begin

-                 gnt_0 <= 0;

-                 state <=  #1  IDLE;

-               end

-    GNT1 : if (req_1 == 1'b1) begin

-                 state <=  #1  GNT2;

-				 gnt_1 <= req_0;

-               end

-    GNT2 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT1;

-				 gnt_1 <= req_1;

-               end

-    default : state <=  #1  IDLE;

- endcase

- end

-

-endmodule


diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys
index a9e94c2..d2b4814 100644
--- a/tests/arch/xilinx/fsm.ys
+++ b/tests/arch/xilinx/fsm.ys

@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 flatten

diff --git a/tests/arch/xilinx/latches.v b/tests/arch/xilinx/latches.v
deleted file mode 100644
index adb5d53..0000000
--- a/tests/arch/xilinx/latches.v
+++ /dev/null

@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule

diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys
index 3eb550a..fe7887e 100644
--- a/tests/arch/xilinx/latches.ys
+++ b/tests/arch/xilinx/latches.ys

@@ -1,4 +1,4 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp

diff --git a/tests/arch/xilinx/logic.v b/tests/arch/xilinx/logic.v
deleted file mode 100644
index e5343ca..0000000
--- a/tests/arch/xilinx/logic.v
+++ /dev/null

@@ -1,18 +0,0 @@
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
-endmodule

diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys
index 9ae5993..c0f6da3 100644
--- a/tests/arch/xilinx/logic.ys
+++ b/tests/arch/xilinx/logic.ys

@@ -1,4 +1,4 @@
-read_verilog logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check

diff --git a/tests/arch/xilinx/mul.v b/tests/arch/xilinx/mul.v
deleted file mode 100644
index d5b48b1..0000000
--- a/tests/arch/xilinx/mul.v
+++ /dev/null

@@ -1,11 +0,0 @@
-module top
-(
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A =  x * y;
-
-endmodule

diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys
index 66a06ef..d768149 100644
--- a/tests/arch/xilinx/mul.ys
+++ b/tests/arch/xilinx/mul.ys

@@ -1,4 +1,4 @@
-read_verilog mul.v
+read_verilog ../common/mul.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check

diff --git a/tests/arch/xilinx/mux.v b/tests/arch/xilinx/mux.v
deleted file mode 100644
index 27bc0bf..0000000
--- a/tests/arch/xilinx/mux.v
+++ /dev/null

@@ -1,65 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule

diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys
index 420dece..821d0fa 100644
--- a/tests/arch/xilinx/mux.ys
+++ b/tests/arch/xilinx/mux.ys

@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2

diff --git a/tests/arch/xilinx/shifter.v b/tests/arch/xilinx/shifter.v
deleted file mode 100644
index 04ae49d..0000000
--- a/tests/arch/xilinx/shifter.v
+++ /dev/null

@@ -1,16 +0,0 @@
-module top    (

-out,

-clk,

-in

-);

-    output [7:0] out;

-    input signed clk, in;

-    reg signed [7:0] out = 0;

-

-    always @(posedge clk)

-	begin

-		out    <= out >> 1;

-		out[7] <= in;

-	end

-

-endmodule


diff --git a/tests/arch/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys
index 84e16f4..455437f 100644
--- a/tests/arch/xilinx/shifter.ys
+++ b/tests/arch/xilinx/shifter.ys

@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten

diff --git a/tests/arch/xilinx/tribuf.v b/tests/arch/xilinx/tribuf.v
deleted file mode 100644
index c644682..0000000
--- a/tests/arch/xilinx/tribuf.v
+++ /dev/null

@@ -1,8 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output reg o;
-    
-    always @(en or i)
-		o <= (en)? i : 1'bZ;
-endmodule

diff --git a/tests/arch/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys
index c9cfb85..4697703 100644
--- a/tests/arch/xilinx/tribuf.ys
+++ b/tests/arch/xilinx/tribuf.ys

@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 tribuf